Invention Grant
US08492901B2 Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof
失效
金属氧化物半导体（MOS）兼容的高纵横比透晶片通孔及其低应力结构
- Patent Title: Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof
- Patent Title (中): 金属氧化物半导体（MOS）兼容的高纵横比透晶片通孔及其低应力结构
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Application No.: US12614062Application Date: 2009-11-06
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Publication No.: US08492901B2Publication Date: 2013-07-23
- Inventor: Bucknell C. Webb
- Applicant: Bucknell C. Webb
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Daniel P. Morris
- Main IPC: H01L23/538
- IPC: H01L23/538
Abstract:
A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.
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