发明授权
US08493107B2 Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
有权
时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
- 专利标题： Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
- 专利标题（中）： 时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
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申请号： US13170197申请日： 2011-06-28
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公开(公告)号： US08493107B2公开(公告)日： 2013-07-23
- 发明人: Robert Bogdan Staszewski , Chi-Hsueh Wang
- 申请人： Robert Bogdan Staszewski , Chi-Hsueh Wang
- 申请人地址： TW Science-Based Industrial Park, Hsin-Chu
- 专利权人： Mediatek Inc.
- 当前专利权人： Mediatek Inc.
- 当前专利权人地址： TW Science-Based Industrial Park, Hsin-Chu
- 代理商 Winston Hsu; Scott Margo
- 主分类号： H03L7/00
- IPC分类号： H03L7/00
摘要：
One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.
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