Invention Grant
US08508993B2 Method and apparatus of performing an erase operation on a memory integrated circuit
有权
在存储器集成电路上执行擦除操作的方法和装置
- Patent Title: Method and apparatus of performing an erase operation on a memory integrated circuit
- Patent Title (中): 在存储器集成电路上执行擦除操作的方法和装置
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Application No.: US13567817Application Date: 2012-08-06
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Publication No.: US08508993B2Publication Date: 2013-08-13
- Inventor: Yi-Fan Chang , Su-chueh Lo , Cheng-Ming Yi , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen Long Chang , Chun Hsiung Hung
- Applicant: Yi-Fan Chang , Su-chueh Lo , Cheng-Ming Yi , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen Long Chang , Chun Hsiung Hung
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
Public/Granted literature
- US20120300553A1 Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit Public/Granted day:2012-11-29
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