发明授权
US08513723B2 Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip
有权
在同一芯片上形成高性能MOS电容器以及完全耗尽的绝缘体上半导体器件的方法和结构
- 专利标题： Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip
- 专利标题（中）： 在同一芯片上形成高性能MOS电容器以及完全耗尽的绝缘体上半导体器件的方法和结构
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申请号： US12689743申请日： 2010-01-19
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公开(公告)号： US08513723B2公开(公告)日： 2013-08-20
- 发明人: Roger A. Booth, Jr. , Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
- 申请人： Roger A. Booth, Jr. , Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Scully, Scott, Murphy & Presser, P.C.
- 代理商 Daniel P. Morris, Esq.
- 主分类号： H01L27/12
- IPC分类号： H01L27/12
摘要：
An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.
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