A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.