Invention Grant
- Patent Title: Method for forming vias in a substrate
- Patent Title (中): 在基板中形成通孔的方法
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Application No.: US12876721Application Date: 2010-09-07
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Publication No.: US08524602B2Publication Date: 2013-09-03
- Inventor: Meng-Jen Wang
- Applicant: Meng-Jen Wang
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: McCracken & Frank LLC
- Priority: TW96128415A 20070802
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.
Public/Granted literature
- US20100330803A1 METHOD FOR FORMING VIAS IN A SUBSTRATE Public/Granted day:2010-12-30
Information query
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