An integrated circuit memory 2 is provided with an array of memory cells 4 and power supply circuitry 10, 12. Detected operating errors in malfunctioning memory cells 14 are identified using a built-in-self-test controller 34. The power supply circuitry 10, 12 is then configured to alter the voltage supply to the malfunctioning memory cells 14 in an attempt to correct their operation. The voltage supply of the row containing the malfunctioning memory cell and the column containing the malfunctioning memory cell may both be altered. The voltage alteration may be an increase or a decrease in voltage supply depending upon the nature of the malfunction detected.