Invention Grant
- Patent Title: Partial write on a low power memory architecture
- Patent Title (中): 部分写低功耗内存架构
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Application No.: US13172592Application Date: 2011-06-29
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Publication No.: US08526264B2Publication Date: 2013-09-03
- Inventor: Anuj Parashar , Marc Vernet
- Applicant: Anuj Parashar , Marc Vernet
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Hogan Lovells US LLP
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.
Public/Granted literature
- US20130003484A1 PARTIAL WRITE ON A LOW POWER MEMORY ARCHITECTURE Public/Granted day:2013-01-03
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