发明授权
US08527928B1 Optimizing circuit layouts by configuring rooms for placing devices
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通过配置放置设备的房间优化电路布局
- 专利标题： Optimizing circuit layouts by configuring rooms for placing devices
- 专利标题（中）： 通过配置放置设备的房间优化电路布局
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申请号： US12655092申请日： 2009-12-23
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公开(公告)号： US08527928B1公开(公告)日： 2013-09-03
- 发明人: Prakash Gopalakrishnan , Alisa Yurovsky
- 申请人： Prakash Gopalakrishnan , Alisa Yurovsky
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Schwegman Lundberg & Woessner, P.A.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.
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