A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.