Invention Grant
- Patent Title: Pattern inspection method and semiconductor device manufacturing method
- Patent Title (中): 图案检查方法和半导体器件制造方法
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Application No.: US13014171Application Date: 2011-01-26
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Publication No.: US08532395B2Publication Date: 2013-09-10
- Inventor: Tadashi Mitsui
- Applicant: Tadashi Mitsui
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2010-118618 20100524
- Main IPC: G06K9/48
- IPC: G06K9/48

Abstract:
In one embodiment, a pattern inspection method is disclosed. The method can include predicting an edge shape at a given future time with respect to the same inspection target pattern, setting a threshold corresponding to a required specification of the inspection target pattern, and predicting the time when the inspection target pattern fails to meet the required specification from the predicted edge shape and the threshold. The method can further include taking a plurality of images concerning the inspection target pattern at different times by use of an imaging apparatus, detecting edges of the obtained images, respectively, matching the detected edges of different imaging times, and obtaining a difference between corresponding edges to generate a difference vector after the matching. The edge shape of the future time can be predicted based on the generated difference vector and an interval between the imaging times.
Public/Granted literature
- US20110286658A1 PATTERN INSPECTION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2011-11-24
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