Invention Grant
US08533521B2 Method for adjusting phase of a clock in a host based upon comparison of first and second pattern signals from a memory and the first and the second pattern signals pre-stored in the host
有权
基于来自存储器的第一和第二图案信号与预先存储在主机中的第一和第二图案信号的比较来调整主机中的时钟的相位的方法
- Patent Title: Method for adjusting phase of a clock in a host based upon comparison of first and second pattern signals from a memory and the first and the second pattern signals pre-stored in the host
- Patent Title (中): 基于来自存储器的第一和第二图案信号与预先存储在主机中的第一和第二图案信号的比较来调整主机中的时钟的相位的方法
-
Application No.: US13619724Application Date: 2012-09-14
-
Publication No.: US08533521B2Publication Date: 2013-09-10
- Inventor: Akihisa Fujimoto
- Applicant: Akihisa Fujimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-334316 20081226
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F1/24 ; G06F11/00
Abstract:
A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
Public/Granted literature
- US20130019119A1 MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD Public/Granted day:2013-01-17
Information query
