Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.