- 专利标题: Reconfigurable equalization architecture for high-speed receivers
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申请号: US13541917申请日: 2012-07-05
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公开(公告)号: US08537886B1公开(公告)日: 2013-09-17
- 发明人: Xiaoyan Su , Sriram Narayan , Sergey Shumarayev
- 申请人: Xiaoyan Su , Sriram Narayan , Sergey Shumarayev
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ropes & Gray LLP
- 主分类号: H03H7/40
- IPC分类号: H03H7/40
摘要:
Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.
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