发明授权
- 专利标题： Systems for single pass parallel hierarchical timing closure of integrated circuit designs
- 专利标题（中）： 集成电路设计的单程并行分层定时闭合系统
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申请号： US13716129申请日： 2012-12-15
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公开(公告)号： US08539402B1公开(公告)日： 2013-09-17
- 发明人: Vivek Bhardwaj , Oleg Levitsky , Dinesh Gupta
- 申请人： Vivek Bhardwaj , Oleg Levitsky , Dinesh Gupta
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Alford Law Group, Inc.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.