Invention Grant
- Patent Title: Top electrode templating for DRAM capacitor
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Application No.: US13665524Application Date: 2012-10-31
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Publication No.: US08541868B2Publication Date: 2013-09-24
- Inventor: Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
- Applicant: Intermolecular, Inc. , Elpida Memory, Inc
- Applicant Address: US CA San Jose JP Tokyo
- Assignee: Intermolecular, Inc.,Elpida Memory, Inc.
- Current Assignee: Intermolecular, Inc.,Elpida Memory, Inc.
- Current Assignee Address: US CA San Jose JP Tokyo
- Main IPC: H01L21/02
- IPC: H01L21/02

Abstract:
A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
Public/Granted literature
- US20130119512A1 Top Electrode Templating for DRAM Capacitor Public/Granted day:2013-05-16
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