Invention Grant
US08546189B2 Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
有权
半导体器件和形成具有顶部和底部焊料凸块互连的晶片级封装的方法
- Patent Title: Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
- Patent Title (中): 半导体器件和形成具有顶部和底部焊料凸块互连的晶片级封装的方法
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Application No.: US12410213Application Date: 2009-03-24
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Publication No.: US08546189B2Publication Date: 2013-10-01
- Inventor: Zigmund R. Camacho , Lionel Chien Hui Tay , Henry D. Bathan , Jeffrey D. Punzalan , Dioscoro A. Merilo
- Applicant: Zigmund R. Camacho , Lionel Chien Hui Tay , Henry D. Bathan , Jeffrey D. Punzalan , Dioscoro A. Merilo
- Applicant Address: SG Singapore
- Assignee: Stats ChipPAC, Ltd.
- Current Assignee: Stats ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/00

Abstract:
A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.
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