A self testing fault circuit interrupter device comprising a fault circuit comprising at least one line monitoring circuit, at least one line interrupting circuit and at least one fault detector circuit which is configured to selectively operate said at least one line interrupting circuit when a fault is detected. This fault circuit also includes at least one test circuit configured to initiate a self test on the fault circuit and at least one timing circuit for controlling the time period for a self test being performed on said at least one self test circuit. The timing circuitry can be in the form of external circuitry which comprises a transistor which controls the discharge rate of a timing capacitor. The timing capacitor is present to prevent any false triggering of a fault circuit. A fault circuit test condition does not stop until the capacitor is fully discharged. By controlling the timing capacitor discharge rate, the triggering of an SCR is not delayed too much in the presence of an external fault because during the presence of this external fault the test cycle is considerably shortened in time based directly upon the size of the external fault. The testing circuit can include a microcontroller which can be programmed to perform a self test across at least two different half cycles of opposite polarity. The determination of the timing of the self test is based upon timing performed by the microcontroller in combination with zero crossing circuitry.