Invention Grant
US08552500B2 Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability
有权
具有多个阈值电压和有源阱偏置能力的CMOS ETSOI的结构
- Patent Title: Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability
- Patent Title (中): 具有多个阈值电压和有源阱偏置能力的CMOS ETSOI的结构
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Application No.: US13114283Application Date: 2011-05-24
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Publication No.: US08552500B2Publication Date: 2013-10-08
- Inventor: Robert H. Dennard , Terence B. Hook
- Applicant: Robert H. Dennard , Terence B. Hook
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.
Public/Granted literature
- US20120299080A1 STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY Public/Granted day:2012-11-29
Information query
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