Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.