A flash memory controller comprises a flash memory interface controller, a host interface controller, a random-access memory (RAM) interface controller, an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to receive a write information datum from the host interface controller and generate an ECC datum. The ECC divider is configured to divide the generated ECC datum into a plurality of ECC segments. The ECC constructor is configured to receive a plurality of ECC segments from the flash memory interface controller and construct an ECC datum. The ECC decoder is configured to correct errors of a read information datum based on a read information datum and the constructed ECC datum and forward the corrected read information datum to the host interface controller when operated in a read mode.