发明授权
US08558229B2 Passivation layer for packaged chip 有权
封装芯片的钝化层

Passivation layer for packaged chip
摘要:
The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
公开/授权文献
信息查询
0/0