发明授权
US08563394B2 Integrated circuit structure having substantially planar N-P step height and methods of forming
失效
具有基本上平面的N-P台阶高度的集成电路结构和形成方法
- 专利标题： Integrated circuit structure having substantially planar N-P step height and methods of forming
- 专利标题（中）： 具有基本上平面的N-P台阶高度的集成电路结构和形成方法
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申请号： US13083631申请日： 2011-04-11
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公开(公告)号： US08563394B2公开(公告)日： 2013-10-22
- 发明人: Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
- 申请人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
- 申请人地址： US NY Armonk KY Grand Cayman
- 专利权人： International Business Machines Corporation,GLOBALFOUNDRIES Inc.
- 当前专利权人： International Business Machines Corporation,GLOBALFOUNDRIES Inc.
- 当前专利权人地址： US NY Armonk KY Grand Cayman
- 代理机构： Hoffman Warnick LLC
- 代理商 Yuanmin Cai
- 主分类号： H01L21/76
- IPC分类号： H01L21/76
摘要：
Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
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