Invention Grant
- Patent Title: Device and method for reducing impedance
- Patent Title (中): 降低阻抗的装置和方法
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Application No.: US11949329Application Date: 2007-12-03
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Publication No.: US08564967B2Publication Date: 2013-10-22
- Inventor: Daniel Irwin Amey, Jr. , William J. Borland
- Applicant: Daniel Irwin Amey, Jr. , William J. Borland
- Applicant Address: US DE Wilmington
- Assignee: CDA Processing Limited Liability Company
- Current Assignee: CDA Processing Limited Liability Company
- Current Assignee Address: US DE Wilmington
- Main IPC: H05K1/16
- IPC: H05K1/16

Abstract:
A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.
Public/Granted literature
- US20090140400A1 Method of Mid-Frequency Decoupling Public/Granted day:2009-06-04
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