Invention Grant
- Patent Title: Methods of modeling a transistor and apparatus used therein
- Patent Title (中): 对其中使用的晶体管和装置进行建模的方法
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Application No.: US13371487Application Date: 2012-02-13
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Publication No.: US08572546B2Publication Date: 2013-10-29
- Inventor: Jaeheon Shin , Woo-Seok Cheong , Chi-Sun Hwang , Sung Mook Chung
- Applicant: Jaeheon Shin , Woo-Seok Cheong , Chi-Sun Hwang , Sung Mook Chung
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2011-0048064 20110520
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.
Public/Granted literature
- US20120297351A1 METHODS OF MODELING A TRANSISTOR AND APPARATUS USED THEREIN Public/Granted day:2012-11-22
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