Invention Grant
- Patent Title: Fabricating method for multilayer printed circuit board
- Patent Title (中): 多层印刷电路板的制造方法
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Application No.: US13585301Application Date: 2012-08-14
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Publication No.: US08574444B2Publication Date: 2013-11-05
- Inventor: Ryoichi Watanabe
- Applicant: Ryoichi Watanabe
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2007-0069275 20070710
- Main IPC: H05K3/00
- IPC: H05K3/00

Abstract:
A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material.
Public/Granted literature
- US20120308718A1 FABRICATING METHOD FOR MULTILAYER PRINTED CIRCUIT BOARD Public/Granted day:2012-12-06
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