An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.