Invention Grant
- Patent Title: Semiconductor stacks including catalytic layers
- Patent Title (中): 包括催化层的半导体堆叠
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Application No.: US13738901Application Date: 2013-01-10
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Publication No.: US08581319B2Publication Date: 2013-11-12
- Inventor: Hanhong Chen , Sandra G. Malhotra , Hiroyuki Ode , Xiangxin Rui
- Applicant: Intermolecular, Inc.
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/94
- IPC: H01L29/94

Abstract:
A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
Public/Granted literature
- US20130140675A1 Method for ALD Deposition Rate Enhancement Public/Granted day:2013-06-06
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