Invention Grant
- Patent Title: Multiplying digital-to-analog converter configured to maintain impedance balancing
- Patent Title (中): 将数模转换器乘以配置为保持阻抗平衡
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Application No.: US13302340Application Date: 2011-11-22
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Publication No.: US08581769B2Publication Date: 2013-11-12
- Inventor: Ashish Kumar , Chandrajit Debnath
- Applicant: Ashish Kumar , Chandrajit Debnath
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Graybeal Jackson LLP
- Main IPC: H03M1/14
- IPC: H03M1/14

Abstract:
A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.
Public/Granted literature
- US20130127646A1 MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (DAC) Public/Granted day:2013-05-23
Information query
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