Invention Grant
- Patent Title: Process variability tolerant programmable memory controller for a pipelined memory system
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Application No.: US13918276Application Date: 2013-06-14
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Publication No.: US08582384B1Publication Date: 2013-11-12
- Inventor: Abhijeet A. Chachad , Ramakrishnan Venkatasubramanian , Raguram Damodaran
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G11C17/18
- IPC: G11C17/18
Abstract:
In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.
Public/Granted literature
- US20130283002A1 Process Variability Tolerant Programmable Memory Controller for a Pipelined Memory System Public/Granted day:2013-10-24
Information query
