Invention Grant
US08583896B2 Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain
有权
具有多个处理元件链的大规模并行处理核和存储从每个链接收的选择数据的各自的智能存储器
- Patent Title: Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain
- Patent Title (中): 具有多个处理元件链的大规模并行处理核和存储从每个链接收的选择数据的各自的智能存储器
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Application No.: US12843579Application Date: 2010-07-26
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Publication No.: US08583896B2Publication Date: 2013-11-12
- Inventor: Srihari Cadambi , Abhinandan Majumdar , Michela Becchi , Srimat Chakradhar , Hans Peter Graf
- Applicant: Srihari Cadambi , Abhinandan Majumdar , Michela Becchi , Srimat Chakradhar , Hans Peter Graf
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Joseph Kolodka; James Bitetto
- Main IPC: G06F15/80
- IPC: G06F15/80
Abstract:
Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.
Public/Granted literature
- US20110119467A1 MASSIVELY PARALLEL, SMART MEMORY BASED ACCELERATOR Public/Granted day:2011-05-19
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