The present invention provides a pseudo random signal generation circuit including: pattern signal output circuit including N stages of D flip-flops (DFF), and that outputs a pattern signal repeating bit patterns of 2N−1 bits from the non-inverting terminal of the final stage DFF; a signal output circuit that outputs a signal expressing the bit pattern length every time 2N−1 bits of the pattern signal are output; a selection signal output circuit that, based on the signal expressing the bit pattern length, outputs a selection signal for repeatedly selecting plural terminals, from plural terminals including the non-inverting terminals and the inverting terminals of the pattern signal output circuit, plural terminals at a time; and an output circuit that selects the signals output from the plural terminals according to the selection signal, and outputs the selected signal as a pseudo random signal.