Invention Grant
US08595437B1 Compression status bit cache with deterministic isochronous latency
有权
具有确定性同步延迟的压缩状态位缓存
- Patent Title: Compression status bit cache with deterministic isochronous latency
- Patent Title (中): 具有确定性同步延迟的压缩状态位缓存
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Application No.: US12276147Application Date: 2008-11-21
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Publication No.: US08595437B1Publication Date: 2013-11-26
- Inventor: David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
- Applicant: David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, L.L.P.
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache improves overall memory system performance by providing on-chip availability of compression status bits that are used to size and interpret a memory access request to compressed memory. To avoid non-deterministic latency when an isochronous memory client accesses the compression status bit cache, two design features are employed. The first design feature involves bypassing any intermediate cache when the compression status bit cache reads a new cache line in response to a cache read miss, thereby eliminating additional, potentially non-deterministic latencies outside the scope of the compression status bit cache. The second design feature involves maintaining a minimum pool of clean cache lines by opportunistically writing back dirty cache lines and, optionally, temporarily blocking non-critical requests that would dirty already clean cache lines. With clean cache lines available to be overwritten quickly, the compression status bit cache avoids incurring additional miss write back latencies.
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