Invention Grant
US08598713B2 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
有权
深硅通孔用于电路和器件的接地,发射极的镇流和隔离
- Patent Title: Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation
- Patent Title (中): 深硅通孔用于电路和器件的接地,发射极的镇流和隔离
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Application No.: US12800663Application Date: 2010-05-20
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Publication No.: US08598713B2Publication Date: 2013-12-03
- Inventor: Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
- Applicant: Volker Blaschke , Todd Thibeault , Chris Cureton , Paul Hurwitz , Arjun Kar-Roy , David Howard , Marco Racanelli
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
Public/Granted literature
- US20110018109A1 Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation Public/Granted day:2011-01-27
Information query
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