A driver for a display may include a first signal processor adapted to output first and third control signals, and a second signal processor adapted to output a second control signal. The first signal processor may include a first shift register adapted to receive clock signals, and a first input signal, and to output a shifted signal. A first logic gate may be adapted to receive the shifted control signal and a separation signal to output the first control signal. A second logic gate may be adapted to receive the shifted signal and a negative separation signal, and to output the third control signal. The second signal processor may include a second shift register adapted to receive clock signals and the second input signal, and to output a shifted signal, and a first inverter adapted to receive the shifted signal of the second shift register and to output a second control signal.