According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y