Invention Grant
US08610174B2 Bipolar transistor with a raised collector pedestal for reduced capacitance
有权
双极晶体管带有集电极基座,用于降低电容
- Patent Title: Bipolar transistor with a raised collector pedestal for reduced capacitance
- Patent Title (中): 双极晶体管带有集电极基座,用于降低电容
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Application No.: US13307412Application Date: 2011-11-30
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Publication No.: US08610174B2Publication Date: 2013-12-17
- Inventor: James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
- Applicant: James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent Michael J. LeStrange, Esq.
- Main IPC: H01L31/109
- IPC: H01L31/109

Abstract:
Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
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