Disclosed is a low mismatch semiconductor device that comprises a lightly doped channel region having a first conductivity type and a first dopant concentration in a semiconductor body, and a high-k metal gate stack including a gate metal layer formed over a high-k gate dielectric without having a dielectric cap on the high-k dielectric. The high-k metal gate stack being formed over the lightly doped channel region. The lightly doped channel region may be a P- or N-conductivity region, for example, and may be part of a corresponding P- or N-semiconductor substrate, or a P- or N-well formed in a substrate of the respectively opposite conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS analog device, for example, can be fabricated as part of an integrated circuit including one or more CMOS logic devices.