发明授权
US08611371B2 Device for generating counter signals representative of clock signals and device for reconstructing clock signals, for a packet-switched network
有权
用于产生表示时钟信号的计数器信号的装置和用于重新构建时钟信号的装置，用于分组交换网络
- 专利标题： Device for generating counter signals representative of clock signals and device for reconstructing clock signals, for a packet-switched network
- 专利标题（中）： 用于产生表示时钟信号的计数器信号的装置和用于重新构建时钟信号的装置，用于分组交换网络
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申请号： US12012694申请日： 2008-02-05
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公开(公告)号： US08611371B2公开(公告)日： 2013-12-17
- 发明人: Thierry Tapie , Serge Defrance , Luis Montalvo
- 申请人： Thierry Tapie , Serge Defrance , Luis Montalvo
- 申请人地址： FR Issy-les-Moulineaux
- 专利权人： Thomson Licensing
- 当前专利权人： Thomson Licensing
- 当前专利权人地址： FR Issy-les-Moulineaux
- 代理机构： Myers Wolin, LLC
- 优先权： FR0753082 20070206
- 主分类号： H04J3/06
- IPC分类号： H04J3/06 ; H04L27/06 ; H03D3/24
摘要：
A device (D2) is dedicated to the reconstruction of clock signals, for example within communication equipment (EQ2) of an IP network. This device (D2) comprises i) a phase-locked loop (BY) having a cut-off frequency dependent, on the one hand, on a configuration value making it possible to reconstruct clock signals according to a chosen clock frequency, and on the other hand, a chosen sampling frequency, and ii) control means (MC2) responsible for forcing the phase-locked loop (BV) to present a variable cut-off frequency according to a received operating mode indication.
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