A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.