Invention Grant
- Patent Title: Method of chip package build-up
- Patent Title (中): 芯片封装的方法
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Application No.: US12843606Application Date: 2010-07-26
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Publication No.: US08623699B2Publication Date: 2014-01-07
- Inventor: Paul Alan McConnelee , Kevin Matthew Durocher , Scott Smith , Laura A. Principe
- Applicant: Paul Alan McConnelee , Kevin Matthew Durocher , Scott Smith , Laura A. Principe
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Agent Jean K. Testa
- Main IPC: H01L21/50
- IPC: H01L21/50

Abstract:
A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
Public/Granted literature
- US20120018857A1 SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP Public/Granted day:2012-01-26
Information query
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