Producing a vertical transistor includes providing a substrate including a gate material layer stack with a reentrant profile. A patterned deposition inhibiting material is deposited over a portion of the gate material layer stack and over a portion of the substrate. An electrically insulating material layer is deposited over a portion of the gate material layer stack and over a portion of the substrate using a selective area deposition process in which the electrically insulating material layer is not deposited over the patterned deposition inhibiting material. A semiconductor material layer is deposited over the electrically insulating material layer.