Invention Grant
- Patent Title: Chip package and fabrication method thereof
- Patent Title (中): 芯片封装及其制造方法
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Application No.: US13802262Application Date: 2013-03-13
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Publication No.: US08633091B2Publication Date: 2014-01-21
- Inventor: Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
- Applicant: Xintec Inc.
- Agency: Liu & Liu
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/301

Abstract:
A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
Public/Granted literature
- US20130196470A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2013-08-01
Information query
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