Invention Grant
US08633537B2 Memory transistor with multiple charge storing layers and a high work function gate electrode
有权
具有多个电荷存储层和高功函数栅电极的存储晶体管
- Patent Title: Memory transistor with multiple charge storing layers and a high work function gate electrode
- Patent Title (中): 具有多个电荷存储层和高功函数栅电极的存储晶体管
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Application No.: US13539466Application Date: 2012-07-01
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Publication No.: US08633537B2Publication Date: 2014-01-21
- Inventor: Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
- Applicant: Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/792
- IPC: H01L29/792

Abstract:
A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.
Public/Granted literature
- US20130307053A1 MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE Public/Granted day:2013-11-21
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