发明授权
- 专利标题: Hardware device for processing the tasks of an algorithm in parallel
- 专利标题(中): 用于并行处理算法任务的硬件设备
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申请号: US13365360申请日: 2012-02-03
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公开(公告)号: US08635620B2公开(公告)日: 2014-01-21
- 发明人: Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
- 申请人: Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Roberts Mlotkowski Safran & Cole, P.C.
- 代理商 Mark Vallone
- 优先权: EP99480050 19990701
- 主分类号: G06F9/46
- IPC分类号: G06F9/46 ; G06F15/76 ; G06F7/38
摘要:
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
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