Invention Grant
- Patent Title: Method of making chip-on-lead package
- Patent Title (中): 芯片引线封装方法
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Application No.: US12727258Application Date: 2010-03-19
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Publication No.: US08642395B2Publication Date: 2014-02-04
- Inventor: Zhe Li , Qingchun He , Guanhua Wang , Zhijie Wang , Nan Xu
- Applicant: Zhe Li , Qingchun He , Guanhua Wang , Zhijie Wang , Nan Xu
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Priority: CN200910130250 20090330
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L21/56 ; H01L33/62
Abstract:
A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.
Public/Granted literature
- US20100248426A1 METHOD OF MAKING CHIP-ON-LEAD PACKAGE Public/Granted day:2010-09-30
Information query
IPC分类:
