发明授权
US08645759B2 Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows
失效
调试机制具有OR电路，用于每当接收到有效控制信号或基于时钟的计数器溢出时触发算术运算数据的存储
- 专利标题： Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows
- 专利标题（中）： 调试机制具有OR电路，用于每当接收到有效控制信号或基于时钟的计数器溢出时触发算术运算数据的存储
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申请号： US12198704申请日： 2008-08-26
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公开(公告)号： US08645759B2公开(公告)日： 2014-02-04
- 发明人: Yoshiteru Ohnuki , Hideo Yamashita
- 申请人： Yoshiteru Ohnuki , Hideo Yamashita
- 申请人地址： JP Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JP Kawasaki
- 代理机构： Staas & Halsey LLP
- 主分类号： G06F11/34
- IPC分类号： G06F11/34 ; G06F17/40
摘要：
A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.
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