Invention Grant
- Patent Title: Method for post decomposition density balancing in integrated circuit layouts, related system and program product
- Patent Title (中): 集成电路布局中后分解密度平衡的方法,相关系统和程序产品
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Application No.: US13596126Application Date: 2012-08-28
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Publication No.: US08647893B1Publication Date: 2014-02-11
- Inventor: Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
- Applicant: Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
Public/Granted literature
Information query
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