发明授权
- 专利标题： Method for post decomposition density balancing in integrated circuit layouts, related system and program product
- 专利标题（中）： 集成电路布局中后分解密度平衡的方法，相关系统和程序产品
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申请号： US13596126申请日： 2012-08-28
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公开(公告)号： US08647893B1公开(公告)日： 2014-02-11
- 发明人: Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
- 申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Hoffman Warnick LLC
- 代理商 Yuanmin Cai
- 主分类号： H01L21/66
- IPC分类号： H01L21/66
摘要：
Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
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