发明授权
- 专利标题: Wafer scribe line structure for improving IC reliability
- 专利标题(中): 晶片刻划线结构,提高IC的可靠性
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申请号: US12054082申请日: 2008-03-24
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公开(公告)号: US08648444B2公开(公告)日: 2014-02-11
- 发明人: Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Yu-Wen Liu
- 申请人: Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Yu-Wen Liu
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater & Matsil, L.L.P.
- 主分类号: H01L21/78
- IPC分类号: H01L21/78
摘要:
A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.
公开/授权文献
- US20090140393A1 WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY 公开/授权日:2009-06-04
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